Current charge-based semiconductor storage technologies such as SRAM, DRAM, NOR flash and NAND flash face scaling challenges as geometries shrink below 20nm. As a result, a marked increase in research activity focused on alternative memory technologies has occurred over the last decade.
Non-charge storage-based memories such as FeRAM and MRAM offer fast RAM-like performance along with non-volatility and extremely high endurance. Although in commercial production, both suffer from high costs vis-à-vis current technologies and have only been able to address niche applications.
All that is likely to change with the availability of samples of in-plane spin-torque transfer MRAM (STT-MRAM) from Avalanche Technology and Everspin Technologies. These achievements are a stepping stone to next generation perpendicular STT-MRAM which promises a scalable path with the potential to broaden its appeal into mainstream consumer applications. As a consequence, the embedded and standalone non-volatile RAM markets are on the cusp of explosive growth in the next few years.
A Magnetic Moment: Prospects for MRAM Technology, Markets and Applications offers an independent view of the opportunities and challenges presented by MRAM technology and its potential as one of the leading contenders in the emerging memory space.

Table Of Contents

Table of Contents


Contents
List of Figures
List of Tables
Executive Summary
Memory Overview
Introduction
The Memory Hierarchy
SRAM
Concept
Technology Evolution
DRAM
Concept
Technology Evolution
NOR Flash
Concept
Technology Evolution
NAND Flash
Concept
Technology Evolution
Ferroelectric Memories
Ferroelectric Random Access Memory (FeRAM)
Ferroelectric Transistors (FeFET)
Phase Change Memory
Concept
Basic Operation
Other Resistive Switching Memories
MRAM
Introduction
Conventional Design
Toggle MRAM
Concept
Materials for the Toggle-MRAM:
Thermal Assisted Switching TAS-MRAM
Concept
Materials for the TAS-MRAM
Spin-Transfer Torque (STT) MRAM
Concept
Materials for the STT
Thermal Stability and Retention
Write Margin vs. Reliability
Scalability
Materials with Perpendicular Magnetic Anisotropy (PMA)
Domain wall (DW) motion MRAM
Concept
Materials for the DW-Motion MRAM Cell
Increasing the Bit Density With Multi Level Cells (MLC)
MLC Based on Single MTJs
MLC Based on Parallel Connected MTJs
MLC Based on Series Connected MTJs
MLC Based on Domain Wall Motion
MLC Programming
Two-Step Programming
Probabilistic Programming
Design and Architecture
STT-MRAM Cell Design
1T-1MTJ
2T-1MTJ
Shared Source-Line (-Plane)
Selection Device
Sensing Schemes
Data Retention Relaxation
Racetrack Memory
MTJ in non-volatile logic
Introduction
Non-volatile Latch/Flip-Flop
Non-volatile Adder
Non-volatile Look-up Table (LUT)
Spin-logic
MRAM Fabrication
Process flow
Element shape
3D Integration
MRAM Cost Drivers
Process Complexity
Cell Efficiency
Yield
Cost per Bit
Memory Comparison
MRAM Characteristics
Switching Time
Current / Power Consumption
Retention Time
Endurance and Wear Leveling
ECC
Scaling
MRAM vs. DRAM
MRAM vs. Flash
MRAM vs. SRAM
MRAM vs. FeRAM
MRAM vs. PCM
Roadmap
MRAM Status
Aeroflex, Inc.
Avalanche Technology
Crocus Technology
Everspin Technologies, Inc.
Freescale Semiconductor
Hitachi Ltd.
Honeywell International, Inc.
IBM Corp.
Infineon Technologies AG
Intel Corp.
Magsil Corporation
Micromem Technologies, Inc.
Micron Technology
NEC Corp.
NVE Corp.
Qualcomm, Inc.
Renesas Technology
Samsung Electronics
SK Hynix Semiconductor
Spin Transfer Technologies
Spingate Technology LLC
SPINTEC
ST Microelectronics
Taiwan Semiconductor Manufacturing Company
Toshiba Corp.
Tower Semiconductor Ltd.
Market and Applications
Introduction
Embedded MRAM Market
Requirement For Successful eMRAM Market Entry
Processor Companion Devices with Battery-backed SRAM and Real-time Clock
Set-top box MCU using EEPROM or Battery-Backed SRAM
RF ID Devices, Smartcards, and e-Passports
Smart Meters
Mobile Baseband SOCs
Mobile Application Processor SoCs
Embedded nvRAM Market Forecast
BB-SRAM
FERAM
nvSRAM
MRAM
Market for nvRAM Product Revenue by Technology
Embedded MRAM Market and Applications Outlook
Standalone MRAM Market
Memory Market Segmentation Based Upon Price/Bit and Feature Sets Differentiation
MRAM as an SRAM Replacement
MRAM as a Non-volatile RAM
RAID Write Index Application
SmartMeter Datalog Application
Other nvRAM Applications
MRAM as a DRAM Replacement
High Density DRAM-compatible MRAM Applications
Instant-on Embedded Controller Memory
RAID Non-volatile Cache Memory
HDD Non-volatile Buffer Memory
Enterprise SSD Metadata Cache/Buffer
Mobile Chipset Memory
MRAM as a Storage Class Memory
Standalone MRAM Market and Applications Summary
References
About the Authors
About Forward Insights
Services
Contact
About NamLab
Contact



List of Figures


Figure 1. Memory Hierarchy
Figure 2. SRAM Cell Schematic
Figure 3. Monolithic 3D SRAM Technology
Figure 4. DRAM Cell Schematic
Figure 5. DRAM Cell Transistor Evolution
Figure 6. DRAM Cell Capacitor Trend
Figure 7. NOR Flash Cell (ETOX: EPROM thin oxide cell)
Figure 8. NOR Architecture
Figure 9. NOR Flash Cell
Figure 10. NOR Flash Technology Evolution
Figure 11. Drain Bias Margin
Figure 12. Multi-bit Charge Trapping Cell
Figure 13. NAND Architecture
Figure 14. NAND Cell String
Figure 15. NAND Flash Technology Evolution
Figure 16. NAND Flash Memory Gap Fill at 63nm and Flat Memory Cell at 20nm
Figure 17. Electrons Stored on the Floating Gate
Figure 18. Operation of a FeRAM Memory
Figure 19. Ferroelectric Field Effect Transistor
Figure 20. Basic PCM Cell Structure and Cell Operation
Figure 21. Resistive Switching Effects
Figure 22. MRAM-Cell Requirements
Figure 23. Schematic View of (a) Field-Induced Switching MRAM and (b) STT MRAM.
Figure 24. MRAM Operation with Field-Induced Switching
Figure 25. Switching Field Threshold for Permalloy Magnetic Elements of Different Ends.
Figure 26. Program Operation in the Toggle Switching Scheme MRAM Design
Figure 27. Toggle-MRAM Cell with a Select Transistor
Figure 28. MTJ Layer Stack and the Uniformity Requirements
Figure 29. Writing Procedure for (a) a Conventional MRAM Cell and (b) TAS MRAM Cell
Figure 30. MTJ Design for a) Conventional Field Driven Approach and b) TAS Approach
Figure 31. Architecture of a TAS-MRAM Memory Array
Figure 32. Influence of the Thickness of an IrMn Layer on the Exchange Bias Field
Figure 33. Area Dependency of the Write Power for a TAS-MRAM Cell
Figure 34. TAS-MRAM Cell Material Stack and Write Power Density vs. Junction Area
Figure 35. Material Stack for a Double Barrier MTJ with one Thermal Barrier
Figure 36. Spin Torque Transfer MRAM Concept
Figure 37. Schematic View of a Typical STT Memory Element and TEM Cross-Section
Figure 38. Illustration of the Spin Polarization Enhancement for a Dual Barrier Structure
Figure 39. Normalized Switching Current Thresholds vs. Magneto-Resistance Ratio
Figure 40. STT-MRAM Write Current Scaling for Different MTJ Structures
Figure 41. Required Room Temperature Values for ?H
Figure 42. Calculated Single Bit Cycle to Cycle Read Error Rate for three ?I Values
Figure 43. Measured Critical Switching Voltage and Break Down Voltage Distributions
Figure 44. Switching Probability vs. Switching Pulse Width
Figure 45. BER Curves Showing a Bifurcated Switching,
Figure 46. Planar MTJ Scaling: Thickness and Switching Current Density vs. Cell Width
Figure 47. Comparison of (a) In-Plane STT-MRAM and (b) Perpendicular STT-MRAM.
Figure 48. Illustration of Perpendicular STT-MRAM Design
Figure 49. Scaling of Critical Switching Current for In-Plane and Perpend. MTJ Elements
Figure 50. Possible Cell Structure and Operation Principle of the DW-Motion MRAM Cell
Figure 51. DW-Motion Cell Structure a) and Cross-Sectional TEM Image b)
Figure 52. DW-Motion Velocity in a Co/Ni Nano-Laminate Free Layer
Figure 53. MLC in Single MTJs - Calculated TMR Ratio
Figure 54. Schematic Illustration of MLC-MTJ
Figure 55. MLC STT-MRAM Cell with Series Connected MTJs
Figure 56. Stacked MTJ Cell Fabrication and Bit Cost Scaling
Figure 57. MLC with Field Compensation Layer
Figure 58. Schematic Representation of MLC Cell Based on Domain Wall Motion
Figure 59. State Transition Graphs of Write Schemes
Figure 60. Probabilistic Programming
Figure 61. 1T-1MTJ STT-MRAM Structure
Figure 62. 2T1MTJ Structure and Layout
Figure 63. Shared SourceLine: a) Schematic and b) Layout
Figure 64. MTJ Current Scaling Compared to the Current Scaling of Select Devices
Figure 65. Non-Destructive Self-Reference Sensing Scheme:
Figure 66. Comparison of Different MTJ Designs at 350K:
Figure 67. Magnetic Racetrack Memory - a 3D Shift Register
Figure 68. The Circuit Diagram of Non-volatile Latch Fabricated by NEC
Figure 69. The Circuit Diagram of Non-volatile Latch Designed by STMicroelectonics
Figure 70. Non-volatile Adder Fabricated by Hitachi.
Figure 71. Non-volatile Lookup-Table Fabricated by Hitcathi
Figure 72. Schematic of Programmable Spin-Logic
Figure 73. MRAM Sputtering Cluster Tools
Figure 74. Schematic Cross Sectional View of an MRAM Module in the Back End Of Line
Figure 75. SEM Cross Section of CMOS Chip with Back End Of Line MTJ MRAM
Figure 76. Top view of MTJ, TEM Cross-Section and Key Process Flow of STT-MRAM
Figure 77. Cross Section of 4Mb MRAM Product and Top-View of the Tunnel Junction
Figure 78. Trade-Off Between Operating Time and Writing Current of the STT-MTJ
Figure 79. Operation of the Proposed Lookback Scheme
Figure 80. Block Diagram of a Cache With Lookback Scheme
Figure 81. Minimum ? (Thermal Stability) Required to Get a 10 Year MTTF.
Figure 82. The Dual-ECC Memory Architecture with Intrinsic and Extrinsic ECCs.
Figure 83. Cell Size Trend
Figure 84. Memory Density Trend
Figure 85. MRAM Papers Presented at VLSI Symposium and IEDM
Figure 86. Everspin 64Mb ST-MRAM Die Photo
Figure 87. 54nm STT-MRAM
Figure 88. OST-MRAM vs. Conventional MRAM
Figure 89. Spingate’s Roadmap and Target Market
Figure 90. Re-write Current Density and MR Ratio
Figure 91. 30-Nanometer Diameter MTJ
Figure 92. Crocus-TowerJazz TAS- MRAM
Figure 93. Device Characteristics
Figure 94. eFlash and NOR Flash Memory Market
Figure 95. MRAM as Converged Embedded Memory
Figure 96. Toggle Mode MRAM Uses Higher Write Power to Generate Magnetic Fields
Figure 97. Spin Torque MRAM Directly Switches MTJ Using Current Through Cell
Figure 98. Cubic Corporation GoCard used eFERAM RF ID Chip
Figure 99. Processor with Hybrid Cache Memory
Figure 100. Market for Embedded nvRAM Products by Technology
Figure 101. Embedded MRAM Value by Application Segment
Figure 102. Standalone Memory Market
Figure 103. Memory Price per MB Trends
Figure 104. Volatile Memory Pyramid
Figure 105. Non-volatile Memory Pyramid
Figure 106. SRAM Market
Figure 107. Battery-Backed SRAM and nvSRAM
Figure 108. RAID Disk Controller Showing RAID Write Journal and Cache Memories
Figure 109. Comparison of HDD Recording Methods
Figure 110. Buffalo’s SSD with MRAM cache
Figure 111. Concept of Storage Class Memory
Figure 113. Price per Megabyte Trend of Conventional and Emerging Memory Technologies
Figure 114. nvRAM Market Forecast
Figure 115. Standalone MRAM Market by Application Segment



List of Tables


Table 1. Comparison of In-Plane and Perpendicular MTJ
Table 2. Comparison of Conventional CMOS Adder and the Non-volatile Adder
Table 3. Estimated Process Complexity for a STT-MRAM Manufacturing
Table 4. Relative Cost Estimation for STT-MRAM Compared to DRAM and NAND Flash
Table 5. Memory Comparison
Table 6. Embedded Memory Roadmap
Table 7. Standalone Memory Roadmap
Table 8. Spingate’s ps-MRAM vs. Other Memory Technologies
Table 9. Key Parameters for eNVM Applications
Table 10. Market for Embedded nvRAM Products by Technology
Table 11. Embedded MRAM Technology and Applications Roadmap
Table 12. Embedded MRAM Revenue and Units by Application
Table 13. Standalone MRAM Technology, Density and Applications Roadmap
Table 14. Price per Megabyte Trend of Conventional and Emerging Memory Technologies
Table 15. Detailed MRAM Forecast (Revenue and Units)

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