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  4. > High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends

The explosion of applications in the consumer and mobile space, internet of things (IoT) and the slowdown of Moore's law have been driving many new trends and innovations in packaging. The semiconductor industry now has to focus on system scaling and integration to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, system power consumption and system cost. This paradigm shift from chip-scaling to system-scaling will re-invent microelectronics, continue driving system bandwidth and performance, and help sustain Moore's Law. The challenge for semiconductor industry is to develop a disruptive packaging technology platform capable of achieving these goals.

This report discusses the packaging trends for higher performance and density driving advanced packaging technology solutions for mobile and IoT applications. One of the key enabling technologies to achieve these goals is thin 3D-packaging with integration. Developments have lately been made with various embedding technologies, such as eWLB/Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.

Table Of Contents

High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends
TABLE OF CONTENTS

Chapter 1 Introduction 1-1

Chapter 2 Executive Summary 2-1

2.1 Summary of Technology Issues 2-1
2.2 Summary of Market Forecasts 2-7

Chapter 3 Technology Issues and Trends 3-1

3.1 Overview of HDP Technology 3-1
3.1.1 Need for Multiple IC Integration 3-7
3.1.2 Challenges of Multiple IC Integration 3-11
3.2 Technical Constraints of Integration 3-12
3.3 Economic Benefits of HDP 3-16
3.4 Technology Issues 3-20
3.4.1 Substrates 3-22
3.4.2 Conductors 3-36
3.4.3 Dielectrics 3-44
3.4.4 Vias 3-46
3.4.5 Die Attachment 3-49
3.4.6 Next Level Interconnection 3-58
3.4.7 Thermal Management 3-60
3.4.8 Test and Inspection 3-62
3.4.9 Design 3-68
3.5 3-D Modules 3-74
3.6 Superconducting Interconnects 3-77
3.7 Known Good Die 3-78
3.8 System In Package (SIP) 3-79
3.9 Multichip Package 3-89
3.10 Package-On-Package (PoP) 3-91

Chapter 4 Applications 4-1

4.1 Semiconductor Industry by End Market 4-1
4.1.1 Application Processors 4-2
4.1.2 Microprocessors 4-7
4.1.3 Programmable Logic Devices (PLDs) 4-14
4.1.4 Analog Devices 4-17
4.1.5 DRAM and NAND 4-19
4.2 Semiconductor Industry by End Market 4-33
4.2.1 Military and Aerospace 4-35
4.2.2 Computer and Peripheral Equipment 4-43
4.2.3 Communications 4-55
4.2.4 Consumer 4-63
4.2.5 Industrial 4-73

Chapter 5 Competitive Environment 5-1

5.1 Overview of the HDP Competitive Environment 5-1
5.2 Joint Ventures and Cooperative Agreements 5-6
5.3 HDP Manufacturers 5-9

Chapter 6 3-D-TSV Technology 6-1

6.1 Driving Forces In 3D-TSV 6-1
6.2 3-D Package Varieties 6-11
6.3 TSV Processes 6-17
6.4 Critical Processing Technologies 6-19
6.4.1 Plasma Etch Technology 6-23
6.4.2 Cu Plating 6-27
6.4.3 Thin Wafer Bondling 6-28
6.4.4 Wafer Thinning/CMP 6-32
6.4.5 Lithography 6-33
6.5 Applications 6-36
6.6 Limitations Of 3-DPackaging Technology 6-42
6.6.1 Thermal Management 6-42
6.6.2 Cost 6-44
6.6.3 Design Complexity 6-45
6.6.4 Time To Delivery 6-50
6.7 Company Profiles 6-51

Chapter 7 Market Forecast 7-1

7.1 Overview of Multichip Modules 7-1
7.2 Driving Forces 7-5
7.3 System-in-Package (SiP) 7-6
7.4 Flip Chip/Wafer Level Packaging 7-13
7.5 Worldwide IC Market Forecast 7-24
7.6 Worldwide Packaging Market Forecast 7-26
7.7 Worldwide MCM Market Forecast 7-28
7.7.1 Worldwide Forecast By Substrate Type 7-33
7.7.2 Worldwide 3-D Through Silicon Via (TSV) Market 7-37


LIST OF TABLES

3.1 Multichip Modules Vs. Circuit Board Assemblies 3-17
3.2 MCM Cost Comparison 3-19
3.3 Substrate Technology Features 3-25
3.4 Metal Conductors in MCMs 3-37
3.5 Comparison of Thin-Film and Thick-Film Technologies 3-40
3.6 Characteristics of Dielectric Materials 3-47
3.7 CTE of Common Substrates and Adhesives 3-56
3.8 Comparison of MCM Testers 3-67
3.9 Density Comparisons of Single Package and 3-D MCM 3-75
4.1 DRAM Supply Forecasts 4-20
4.2 DRAM Demand Forecasts 4-21
4.3 DRAM Demand Forecasts 4-22
4.4 NAND Supply Forecasts 4-28
4.5 NAND Demand Forecasts 4-29
4.6 NAND Demand Forecasts 4-30
4.7 PC Unit Shipment Forecast 4-46
5.1 MCM Manufacturers 5-10
6.1 3-D Mass Memory Volume Comparison Between Other 6-5
Technologies and TI's 3D Technology In Cm3/Gbit
6.2 3-D Mass Memory Weight Comparison Between Other 6-6
Technologies and TI's 3D Technology In Grams3/Gbit
6.3 Institutions Working In The Area Of 3D TSV 6-16
6.4 Companies Working In The Area OF 3D TSV 6-17
7.1 Worldwide IC Package Market Forecast 7-27
7.2 Worldwide MCM Market 7-36


LIST OF FIGURES

1.1 Schematic Cross-Section View Of An MCM-D 1-3
1.2 Cross-Section Of The RF And Microwave MCM-D Structure 1-5
1.3 Thin Film Layers On The Planarized Core Layer Of MCM-SL/D
Technology 1-8
1.4 Flip Chip MCP 1-11
1.5 SIP Cross Section 1-14
3.1 IC Packaging Trends 3-2
3.2 Technology Tree For HDP Types 3-3
3.3 Form Factor Decrease By Package Type 3-10
3.4 High Power Package Technology Roadmap 3-34
3.5 Comparison Between Wire Bonding And Bump 3-51
4.1 PoP 3chipstack Package 4-3
4.2 Application Processor Revenue 4-6
4.3 MPU Unit Shipments And Growth Trends 4-8
4.4 ASIC and ASSP Design Starts 4-14
4.5 PLD Share of Revenue by End Market 4-16
4.6 Analog IC Revenue 4-18
4.7 FCFBGA Memory Package 4-14
4.8 FBGA 2-Chip Memory Package 4-26
4.9 FBGA QDP Memory Package 4-32
4.10 Semiconductor Unit Demand By End Market 4-34
4.11 Military and Aerospace Semiconductor Revenue 4-42
4.12 Computing (Data Processing) Semiconductor Revenue 4-47
4.13 PC Price Decline Over The Past 10 Years 4-48
4.14 Notebooks Declined For The First Time In 2012 4-49
4.15 Tablets Surpassed 100 Million Units In 3 Years 4-51
4.16 Comparison of desktop, notebook, and tablet shipments 4-52
4.17 Server shipments 4-54
4.18 Wireless semi revenue 4-59
4.19 Smartphone shipments 4-60
4.20 Silicon Content Of Mobile Phones 4-62
4.21 Consumer Semi Revenue 4-67
4.22 Average Semi Content By Application 4-69
4.23 Automotive Semiconductor Revenue 4-70
4.24 Automotive Semiconductor Growth 4-72
6.1 3-D Through-Silicon Via (TSV) 6-3
6.2 Silicon Efficiency Comparison Between 3D Packaging 6-8
Technology And Other Conventional Packaging Technologies
6.3 Comparison Between 2D And 3D Packaging Interms Of The 6-9
Accessability And Useablity Of Interconnection
6.4 3D Packages 6-10
6.5 Through-Silicon Via (TSV) 6-18
6.6 Moore's Law For Active Element Density 6-25
7.1 Various System-In-Package (SiP) Applications 7-7
7.2 SiP Structures 7-10
7.1 Comparison Of SOC, MCM, SIP, And SOP 7-8
7.2 Materials Integrated In The SOP Concept 7-11
7.3 Wire Bond Versus Flip Chip 7-17
7.4 Flip Chip And Wire Bond Equipment Forecast 7-19
7.5 Growth In Copper Wire Bonding 7-20
7.6 WLP Demand By Devices 7-22
7.7 WLP Demand By Wafers 7-23
7.8 Projection of 3-D TSV Applications And Process Requirement 7-39
7.9 Market Forecast of 3-D TSV Units 7-40
7.10 Market Forecast of 3-D TSV Wafers 7-41


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