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Ericsson RBS6000 Digital Units ASICs Report

  • July 2015
  • -
  • EJL Wireless Research LLC
  • -
  • 144 pages

This report provides a comprehensive technology analysis of the digital baseband unit ASICs within the Ericsson RBS6000 base station platform. The ASICs analyzed are used in the following Ericsson digital units: DUG 10, DUG 20, DUW 10, DUW 20, DUW 30, DUL 20, DUS 31, and DUS 41. There is a total of six Ericsson baseband ASICs contained within this report.

Features

- Wafer Fabrication ID, Silicon process node ID, Die Size and Package Analysis
- Die photograph, magnified SEM photographs, X-Ray photographs
- Die mapping of functional blocks
- Die mapping of I/Os
- Die mapping of memory structures
- Digital unit system architecture
- DSP core analysis
- Proprietary technology analysis
- Total Pages: 157
- Total Tables: 26
- Total Exhibits: 163

Table Of Contents

Ericsson RBS6000 Digital Units ASICs Report
TABLE OF CONTENTS
EXECUTIVE SUMMARY 7
DU Board Teardowns + ASIC RE Analysis = Invaluable Insight ...... 7
Radio System Architecture History...... 7
BTS Hardware Development Compared with Software Development .. 8
Key Takeaways: Carrier Grade Cost Structure Pressure........10
CHAPTER 1: ERICSSON RADIO SYSTEM ARCHITECTURE 11
1.1 DU Boards and their ASICs .....11
1.2 Ericsson Radio System Architecture..12
1.3 SOFTWARE-DEFINED RADIO ...13
1.4 Multi-standard RAN Complexity........14
1.5 All RAN Ericsson Radio System (ERS)17
1.6 DU ASIC CHART Overview ......19
CHAPTER 2: DIGITAL UNIT (DU) OVERVIEW............ 20
2.1 DU System-Level Architecture Support for ASICs.......20
2.2 DU Board-Level Architecture ...22
2.3 DUG Subsystem...........26
2.4 DUW Subsystem..........27
2.5 DUL and DUS Subsystem .......29
2.6 Common Operation and Maintenance (OandM) Features31
2.7 Board/ASIC Trace and Debug Overview33
CHAPTER 3: RBS DIGITAL UNIT (DU) PROCESSING... 39
3.1 DU Analysis Scope/Process .....39
3.2 DUL/DUS Subsystem Functionality...........42
3.3 In-depth ASIC Analysis Process........43
3.4 Multi-Core Ecosystem...48
3.5 Atypical Trace and Debug Capabilities..51
3.6 DU Architectural Summary .....52
CHAPTER 4: DU ASIC OVERVIEW. 53
4.1 ASIC Process Nodes..53
4.2 ASIC Fabrication Source Analysis55
4.3 Silicon Area and Function .......58
4.4 DSP/Multi-Core Evolution .......58
CHAPTER 5: MULTI-CORE/DSP OVERVIEW. 61
5.1 Shift from PowerPC? to ARM Ecosystem......61
5.2 DSP Core Technology/Analysis 63
5.3 Internal DSP Cores.......63
CHAPTER 6: DUG ASICS FOR GSM. 69
6.1 GSM Processing Overview.......69
6.2 Basic Structure and Architecture......70
6.3 I/O Analysis...76
6.4 DUG ASIC-2 Summary of findings............76
CHAPTER 7: DUW ASICS FOR W-CDMA.. 77
7.1 DUW ASICs Overview...77
7.2 DUW ASIC #1 Package Analysis.......80
7.3 DUW ASIC #1 Chip Analysis ...80
7.4 DUW ASIC #1 Functional Analysis....84
7.5 DUW ASIC #2 Package Analysis.......85
7.6 DUW ASIC #2 Chip Analysis ...86
7.7 DUW ASIC #2 Special Structures91
2
Licensed to First Name Last Name, Company Name
© 2015 EJL Wireless Research LLC. All Rights Reserved
CHAPTER 8: DUL ASIC ANALYSIS 93
8.1 DUL ASIC Overview......93
8.2 DUL ASIC Package Analysis ....94
8.3 DUL ASIC Chip Analysis95
8.4 DUL ASIC CPU Functions ......101
8.5 DSP Functions...........106
8.6 Digital and Analog I/Os ........111
CHAPTER 9: DUS ASIC ANALYSIS. 116
9.1 DUS ASIC Overview116
9.2 DUS ASIC Package Analysis ..117
9.3 DUS ASIC Chip Analysis .......117
9.4 Evolution from Previous ASICs.......122
9.5 Core Processor Functions......128
9.6 DUS DSP Complex..131
9.7 Special Structures, Digital and Analog I/Os136
9.8 Other DUS ASIC Proprietary Technology Analysis.....145
CHAPTER 10: CONCLUSION. 153

TABLES

Table 1: Ericsson BTS ASICs and Digital Unit (DU) Hardware.7
Table 2: Six Major Ericsson Digital Baseband Processing ASICs............ 19
Table 3: Ericsson DUG, DUW, DUL and DUS ASIC Silicon Chart............ 39
Table 4: Ericsson DUG, DUW, DUL and DUS ASIC Software Chart. 40
Table 5: Ericsson DU DSP Block Area Chart; from DUG, DUW, DUL and DUS ASICs 59
Table 6: Essential RT/Embedded Communications Proprietary Technology............ 61
Table 7: Ericsson BTS ASIC and Digital Unit (DU) Hardware Components. 79
Table 8: DUL Chip/ASIC Proprietary Technology Overview .. 99
Table 9: DUL ASIC Cortexâ„¢-R MPCoreâ„¢ Memory/Register Overview...... 102
Table 10: DUL ASIC ETMâ„¢-R4/R5 Register/Memory Overview..... 102
Table 11: ETMâ„¢-R4/R5 Register/Memory Count...... 103
Table 12: ARM Cortexâ„¢-R5 Dual/MPCoreâ„¢ Area Analysis .. 105
Table 13: DUL ASIC DSP Core Overview S 106
Table 14: DUL ASIC Digital and Analog I/Os........... 112
Table 15: DUS ASIC's Memory Cell Types. 120
Table 16: Comparing DUL/DUS ASIC's ARM Cortexâ„¢-R MPCoreâ„¢ Memory Blocks.. 123
Table 17: Comparing ARM Proprietary Technology in DUL/DUS ASICs. 124
Table 18: Comparing I/O and I/O Subsystems in DUL and DUS ASICs... 127
Table 19: Comparing ARM Proprietary Technology in DUL/DUS ASICs. 128
Table 20: DUS ASIC DSP Area 1 and 2 Memory Blocks ..... 131
Table 21: DUS ASIC DSP H Block Detail.... 134
Table 22: DUS E Block Ethernet Memory and Buffer Structures.......... 148
Table 23: DUS F Block Memory Structure Analysis.. 149
Table 24: DUS ASIC G Block Detail 151
Table 25: DUS ASIC “K” Block....... 152
Table 26: Ericsson Radio System Architectural BTS Roadmap Requirements.. 154


EXHIBITS

Exhibit 1: Ericsson BTS System Hardware and Software Release, 2003-2016..........8
Exhibit 2: BTS System Hardware, Software, and Service Revenue Priority 10
Exhibit 3: RBS 6000 Architecture showing “Digital Units” with RUs and RRUs........ 11
Exhibit 4: RBS 6000 Architecture showing Digital Units (Center Bottom).. 12
Exhibit 5: Multi-RAT RAN according to Ericsson..... 13
Exhibit 6: GSM RAN as part of the Multi-Standard ERS ....... 14
Exhibit 7: W-CDMA RAN as part of the Multi-Standard ERS . 15
Exhibit 8: LTE RAN as part of Multi-Standard ERS..... 16
Exhibit 9: Multiple Standards in a BTS. 16
Exhibit 10: Ericsson Radio System BTS RBS 2000/3000 and RBS 6000 Evolution... 17
Exhibit 11: Example of DU Multi-standard Mix Mode System Support...... 18
Exhibit 12: Digital Unit - Generic Ericsson DU Block Diagram....... 20
Exhibit 13: Digital Unit Software Architectural Mapping....... 21
Exhibit 14: Mapping Basic LTE Software Functions to Hardware Proprietary Technology Cores .. 21
Exhibit 15: Digital Unit - Generic Ericsson DU Block Diagram....... 22
Exhibit 16: Baseband Digital Unit - ERS Baseband DUS XX Block Diagram............ 23
Exhibit 17: Software Layers with RT (Real-Time) Extensions........ 24
Exhibit 18: LTE Layer Multi-core SoC Software - Core and DSP..... 25
Exhibit 19: Protecting the RBS 6000 Investment... 26
Exhibit 20: DUG 20 01 - Front Panel 26
Exhibit 21: DUG 20 01 - Board (Top View) with Heatsinks .. 27
Exhibit 22: DUW 20 01 - Front Panel......... 28
Exhibit 23: DUW 10, DUW 20, DUW 30, DUW 11, DUW 31, and DUW 41 versions.. 28
Exhibit 24: DUW RF/IF board and the Baseband I/O Board.. 28
Exhibit 25: DUL 20 01 - Front Panel markings, ports, and indicators 29
Exhibit 26: DUS 31 01/DUS 41 01 - Front Panel....... 29
Exhibit 27: Top View DUL 20 01 Board 30
Exhibit 28: DUS 41 01 Board Bottom View (L) and Top-View (R).. 31
Exhibit 29: Direct to DU ASIC Equipment and Managed Objects w/LMT port.......... 31
Exhibit 30: Ericsson DU Support Management System and the MOM 32
Exhibit 31: OSS-RC CPI Active Library Explorer (ALEX) Access..... 33
Exhibit 32: Ericsson DU ASIC Prototype Verification and Extended Trace Options... 34
Exhibit 33: Ericsson DU ASIC Documentation Match to DUL ASIC......... 35
Exhibit 34: DUL ASIC Identified ROM and Register Structures. 36
Exhibit 35: Debug Ports on DUL board with a Serial GigaBit Trace Interface.......... 37
Exhibit 36: Processor Debug Ports on DUL board with a Serial GigaBit Trace Interface... 37
Exhibit 37: DU ASIC Structures: CoreSightâ„¢ Embedded Trace Macrocellâ„¢............ 38
Exhibit 38: DUL Package differences between “R1A” and “R2A” ASIC Revisions 40
Exhibit 39: Ericsson RBS 6000 DU ASICs.... 41
Exhibit 40: Ericsson DUG, DUW, DUL, and DUS ASICs ........ 42
Exhibit 41: Ericsson DUS ASIC Revisions.... 42
Exhibit 42: Software/OS Proprietary Technology: Multi-Standard LTE Macrocell Example 2012 . 43
Exhibit 43: Software/OS Boot Device Loading and Booting ASIC Devices. 44
Exhibit 44: Software/OS Proprietary Technology: Fixed 3GPP LTE RAN Processing Requirements ........... 45
Exhibit 45: Software/OS Proprietary Technology: Multi-Standard RAN..... 46
Exhibit 46: DUx Address and ASIC MO Mapping........ 46
Exhibit 47: Software/OS: Software/Hardware Driver Layering...... 47
Exhibit 48: Software/OS Proprietary Technology: Multi-Standard RAN..... 47
Exhibit 49: Illustrative BTS DU-ASIC Baseband Architecture 48
Exhibit 50: CEVA DSP Complex with ARM and CEVA CoreSightâ„¢.......... 49
Exhibit 51: ARM Cortexâ„¢-R7 MPCoreâ„¢ and CEVA XC4000 Proprietary Technology. 50
Exhibit 52: Ericsson DUW, DUL, and DUS ASIC Processor/DSP Test Headers......... 51
Exhibit 53: Shared DUW and DUL ASIC Structures.... 52
Exhibit 54: ASIC Process Node Identification............ 53
Exhibit 55: ASIC Process Node Identification............ 54
Exhibit 56: ARM 65LPe Low Power Physical Platform........... 54
Exhibit 57: Ericsson DUW and DUL ASIC Process Technology.. 56
Exhibit 58: TSMC ASIC Fabrication Technology......... 57
Exhibit 59: Ericsson DU ASIC Processor Area Comparison ... 58
Exhibit 60: Ericsson DU ASIC DSP Block Comparisons ........ 59
Exhibit 61: Ericsson DUW ASIC Logic-Based Computation Example.. 60
Exhibit 62: DUS ASIC RapidIO? Buffer 62
Exhibit 63: DSP Proprietary Technology Block Evolution in Ericsson DU ASICs: 2003 to 2011 ... 63
Exhibit 64: SoC and ASIC Design Philosophy at Ericsson (circa 2014).. 65
Exhibit 65: DSP Core Hardware/Software Tradeoff Example for Ericsson DUW ASIC Design...... 66
Exhibit 66: DSP PSU (Power-Scaling Unit) Proprietary Technology........ 67
Exhibit 67: Die Size Progression in the Ericsson DUG, DUW, DUL, and DUS ASICs............ 68
Exhibit 68: DUG ASICs #1 and #2... 69
Exhibit 69: DUG ASIC #1 Markings.. 70
Exhibit 70: DUG ASIC #1 PowerPC? Core... 70
Exhibit 71: Digital Unit for GSM-DUG 20 01 Front Panel and Mechanical... 72
Exhibit 72: DUG Diagram and Typical Multi-RAT RBS 6000 Use............ 72
Exhibit 73: DUG Block Diagram....... 73
Exhibit 74: DUG ASIC #2 Markings.. 73
Exhibit 75: Digital Unit for GSM-DUG ASIC #2 Overview ..... 74
Exhibit 76: DUG ASIC #2 DSP Core........... 75
Exhibit 77: DUG ASIC #2 Dual PowerPC? Core..... 75
Exhibit 78: DUG ASIC #2 Processor Core Complex w/PLL.... 76
Exhibit 79: RBS 6000 DUW Architecture featuring DUW ASICs #1 and #2............ 77
Exhibit 80: DUW Front Panel and Mechanical.. 78
Exhibit 81: DUW ASIC #1 Package Overview............ 80
Exhibit 82: DUW ASIC #1 Package X-Ray... 80
Exhibit 83: DUW ASIC #1 Top Metal Layer with Magnified Views of the Die Logo and I/O Pads . 81
Exhibit 84: 256-tap FIR Filter Performance examples; Logic and DSP computation. 82
Exhibit 85: DUW ASIC #1 Si Poly Overview. 82
Exhibit 86: DUW ASIC #1 Poly Layout SEM. 83
Exhibit 87: DUW ASIC #1 Memory Structure Decomposition........ 84
Exhibit 88: DUW ASIC #1 Memory Structures A-F Block Decomposition... 84
Exhibit 89: DUW ASIC #2 Package Overview............ 85
Exhibit 90: DUW ASIC #2 Package X-Ray... 85
Exhibit 91: DUW ASIC #2 Die Overview and Markings ........ 86
Exhibit 92: DUW ASIC #2 Main Feature Overview..... 87
Exhibit 93: DUW ASIC #2 I/O Match ULMA I/O Subsystems 88
Exhibit 94: DUW ASIC #2 Processing Technology.. 88
Exhibit 95: DUW ASIC #2 Analog Power Block.......... 89
Exhibit 96: DUW ASIC #2 I/O Structures.... 89
Exhibit 97: DUW ASIC #2 Special Power Management Structures. 90
Exhibit 98: DUW ASIC #2 Special Structure 91
Exhibit 99: DUW ASIC #2 DSP Core Structures vs. DUL ASIC DSP Core Structures 92
Exhibit 100: DUW ASIC #2 Memory Bit-Cell Comparison to DUL ASIC..... 92
Exhibit 101: DUL ASIC Board-Level Overview........... 93
Exhibit 102: DUL ASIC Package Revisions... 94
Exhibit 103: DUL ASIC Package X-ray with Side-View 94
Exhibit 104: DUL ASIC Package Information.. 95
Exhibit 105: DUL ASIC Die Size and Top Metal Layer. 95
Exhibit 106: DUL ASIC Die Markings.......... 96
Exhibit 107: DUL ASIC Block Overview; DSP Cores, Analog, and I/O Blocks.......... 98
Exhibit 108: DUL ASIC Si Structures. 100
Exhibit 109: DUL ASIC Cortex-R MPCoreâ„¢ Layout Detail ... 101
Exhibit 110: Suspected ARM CoreSightâ„¢-based ETMâ„¢ ...... 103
Exhibit 111: DUL ASIC Cortexâ„¢-R5 Dual/MPCoreâ„¢ Analysis....... 104
Exhibit 112: ARM Cortexâ„¢-R5 Dual/MPCoreâ„¢ Area Analysis....... 105
Exhibit 113: Comparison of ARM Cortexâ„¢-R5 Area to Known Cortexâ„¢-R4 Chip..... 106
Exhibit 114: DUL ASIC DSP Core 1. 107
Exhibit 115: DUL ASIC DSP Core 2. 108
Exhibit 116: DUL/DUS ASIC DSP Control Logic....... 109
Exhibit 117: DUL ASIC DSP Control Logic and PSU.. 110
Exhibit 118: DUL ASIC I/O Overview. 111
Exhibit 119: Primary DUL ASIC Analog Block AN3 Overview....... 112
Exhibit 120: Primary DUL ASIC Analog Block AN2 Overview....... 113
Exhibit 121: DUL ASIC Analog Block AN1 Overview. 113
Exhibit 122: Primary DUL Analog Blocks Overview.. 114
Exhibit 123: DUL ASIC #2 Temperature Sensor Detail ...... 115
Exhibit 124: DUS ASIC Board-Level Overview..... 116
Exhibit 125: DUS ASIC Package and Die Overview.. 117
Exhibit 126: DUS ASIC OM, Plan-view, Top, with Die Markings... 118
Exhibit 127: DUS ASIC SEM Cross Section (Seal Ring)...... 118
Exhibit 128: DUS ASIC Memory Types...... 120
Exhibit 129: DUS ASIC Overview showing ARM Cortexâ„¢-R7 MPCoreâ„¢ and major blocks .. 121
Exhibit 130: DUL/DUS ASIC DSP Cores Comparison 121
Exhibit 131: DUS ASIC Block Overview; Areas 1 to 5, Analog, and Blocks A-X..... 122
Exhibit 132: Comparison of DUW and DUL ASICs to the DUL ASIC. 124
Exhibit 133: Comparison of ARM Cortexâ„¢-R5 Dual Core to ARM Cortexâ„¢-R7 MPCoreâ„¢.. 125
Exhibit 134: Evolution of DSP Complex in DUL and DUS ASICs... 126
Exhibit 135: Cortexâ„¢ R-7 MPCoreâ„¢ ETMâ„¢.. 128
Exhibit 136: DUS ASIC Cortexâ„¢ R-7 MPCoreâ„¢ Block Overview.... 129
Exhibit 137: DUS ASIC DSP Area 1 and 2 Overview.......... 131
Exhibit 138: ARM/CEVA DSP Complex in DUS ASIC. 132
Exhibit 139: ARM/CEVA Proprietary Technology Block Diagram in the DUS ASIC.. 133
Exhibit 140: DUS ASIC “H” Block - DSP Subsystem 135
Exhibit 141: DUS ASIC Analog/SerDes I/O 136
Exhibit 142: DUS ASIC Analog Structure Overview........... 137
Exhibit 143: DUS ASIC X-Block Detail and Substructures .. 138
Exhibit 144: DUS ASIC Digital I/O Blocks Detail, 1-12 ...... 138
Exhibit 145: Analog block 1 (AN1) and 3 (AN3) with X-block detail 139
Exhibit 146: DUS ASIC 2- and 4-lane Switch Structures.... 140
Exhibit 147: DUS ASIC ROM and ARM Core Overview ....... 141
Exhibit 148: DUS ASIC Area 3: ARM Core A3 Block Overview..... 142
Exhibit 149: DUS ASIC Area 4: ARM Cortex-A* A4 Block Overview..... 143
Exhibit 150: DUL ASIC I/O Overview. 144
Exhibit 151: DUS ASIC Digital I/O Blocks Detail, 1-12 ...... 144
Exhibit 152: DUS ASIC B and D Block Switch Structure Overview.. 145
Exhibit 153: DUS ASIC B Block Switch Structure Detail..... 145
Exhibit 154: DUS Buffer Memory Block..... 146
Exhibit 155: DUS ASIC D Block Switch Structure Detail .... 146
Exhibit 156: DUS ASIC Analog AN2 and its E Block Controller..... 147
Exhibit 157: DUL ASIC E Block for Ethernet Control and Management... 147
Exhibit 158: DUL ASIC F Block Overview.. 149
Exhibit 159: DUS ASIC G Block - RapidIO? Subsystem .... 150
Exhibit 160: DUS ASIC G Block Structure Overview.......... 150
Exhibit 161: DUS ASIC “G” Block Structure Detail... 151
Exhibit 162: DUS ASIC “K” Block Structure Overview ....... 152

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