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Reverse Costing of Samsung M393A8G40D40 DRAM with TSV

  • July 2015
  • -
  • System Plus Consulting
  • -
  • 100 pages

Executive Summary
This full reverse costing study has been conducted to provide insight on technology data, manufacturing cost and selling price of the Samsung 3D TSV Stacked DRAM PRocess.
- 3D TSV technology is expected to reach $4.8B in revenues by 2019, mainly driven by 3D stacked DRAM and followed by 3D Logic/Memory and Wide I/O according to Yole Développement.
- With 40% share in the DRAM market, Samsung is by far the number 1 player. By introducing 3D TSV stacking in their latest 64GB DDR4, Samsung allows this technology to enter in the main stream.
- This registered dual Inline memory module (RDIMM) includes 36 DDR4 DRAM chips (ref. K4AAG045WD), each of which consists of four 4Gb DDR4 DRAM dies (Ref. K4A4G085WD). The chips are manufactured using Samsung’s 20nm process technology and 3D TSV via-middle package technology.
- As a result, the new 64GB TSV module performs twice as fast as a 64GB module that uses wire bonding packaging, while consuming approximately half the power.
- On the process side, Samsung used a temporary bonding approach using adhesive glue material and copper via-filled using bottom up filling. Also, System Plus paid particular attention in identifying all
technical choices made by Samsung on process and equipment (wafer bonding, DRIE via etching, via filling, bumping, underfill…).
- The report includes a complete physical analysis and cost estimation of the 3D packaging process, as well as a detailed description of the manufacturing process.

Table Of Contents

Reverse Costing of Samsung M393A8G40D40 DRAM with TSV
Glossary
1. Overview / Introduction 4
- Executive Summary
- Reverse Costing Methodology
2. Company Profile 7
- Samsung Electronics
3. Physical Analysis 12
- Synthesis of the Physical Analysis
- Physical Analysis Methodology
- Module 15
- RDIMM Module Views and Dimensions
- Package 19
- View, Dimensions and Marking
- Package Opening
- Package PCB Line/Space
- DRAM Die 26
- View, Dimensions and Marking
- Bond Pads and TSVs
- Die Delayering
- TSV Details
- Cross-Section 36
- Package Cross-Section
- Micro-bumps Cross-Section
- TSV Cross-Section
- Flip-Chip Bumps Cross-Section
4. Manufacturing Process Flow 61
- Global Overview
- TSV and Bumping Process Flow
- Flip-Chip and Stacking Process Flow
- Package Assembly Unit
6. Cost Analysis 77
- Main steps of economic analysis
- Yields Hypotheses
- DRAM Front-End Cost
- TSV Manufacturing Cost
- TSV Manufacturing Cost per Process Steps
- Micro-Bumping Manufacturing Cost
- Micro-Bumping Cost per Process Steps
- Flip-Chip Bumping Manufacturing Cost
- Flip-Chip Bumping Cost per Process Steps
- DRAM Die Cost
- Final Packaging Cost
- Final Packaging Cost per Process Steps
- Component Cost
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