WLP and Embedded Die Market - Technologies 2008
If we take a look at the amazing learning curve of the semiconductor industry in terms ofchip density versus cost improvements over time, it is easy to realize that a gap iswidening between the scaling evolutions of the chip front-end and the packagingassemblymanufacturing industries.Wafer level packaging (WLP) is all about filling that gap by making the packaging andassembly steps a whole collective wafer level process. Packaging has now the potential toscale with the cost and size evolutions of most stringent semiconductor applications. Asa generic description, WLP shouldbe defined as “all packaging andassembly process steps are doneat the wafer level, the last stepbeing the chip dicing”.Subsequently, WLP does notrequire any intermediate substrateinterposer: wafer level packagedcomponents are directly “surfacemountable” onto the circuit board.WLP is definitively a breakthroughtechnology to be diffused even intothe most cost sensitiveapplications as it will scalefavorably to the trend tomanufacture on ever increasingwafer diameters.Actually, it is difficult to estimate what is the real status of volume production for WLP. Thisnew packaging report aims at giving clues to understand technologies, trends and marketstatus of WLP in Semiconductor ICs, CMOS imagers and MEMS applications.
“WLP & Embedded Die Technologies 08” report presents:
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